Demand for NAND type flash memory is increasing rapidly along with the increase in applications handling large volumes of data such as photographic images and moving images in mobile appliances, and the like. In particular, the adoption of multilevel storage technology enabling two bits or more of information to be stored in one memory cell makes it possible to store a greater amount of information in a small chip area.
As number of levels in the multilevel storage technology increases, the margin between threshold voltage distributions in memory cells narrows, hence it becomes necessary to control each of the threshold voltage distributions more narrowly. One technique for achieving this is a method where write voltages are applied to the memory cells by dividing the write voltages into a plurality of pulses having pulse heights that increase stepwise. Also known is a high-speed pass write system and so on, where two stages of write verify reads are performed during data write. However, with increasing miniaturization, there is a problem that, even if these systems are adopted, effects of program noise due to write voltage application cause variation in the amount of threshold shift in memory cells, whereby threshold voltage distributions become larger.